Fixing a Planar Problem

For the past several years, the industry has been transitioning to high k metal gate (HKMG) transistors in high-performance logic chips. It’s been a tough engineering challenge requiring extensive research into new materials and production processes. But today, HKMG transistors are successfully being produced in high volume manufacturing for advanced logic devices.

At this year’s Advanced Semiconductor Manufacturing Conference, I presented one of the technologies that is enabling this higher performance future. It involves a key issue for the replacement metal gate approach to implementing HKMG. The replacement metal gate method, first announced by Intel in 2007, is now being adopted by other semiconductor companies. One advantage of the replace metal gate method is that it doesn’t require high temperature processes after the gate has been formed that can adversely impact device reliability and voltage shifts. However, this method does present challenges in planarization, which is usually done with a chemical mechanical planarization (CMP) system.

The requirements for within-wafer, within-die and wafer-to-wafer thickness variations of the crucial inter-layer dielectric level zero (ILD0) CMP step are extremely stringent. Traditional CMP processes that use high selectivity slurry cannot meet these tighter planarity requirements.

A revolutionary approach is needed, and the solution was found with Applied Materials’ Fixed-Abrasive (FA) polishing technology. Polishing characteristics of FA include exceptionally low dishing, minimal nitride loss and process repeatability. We have a FA solution for ILD0 that has demonstrated excellent post-CMP planarity in HKMG manufacturing. For more on this solution, I invite you to view the recap video.