Semiconductors

It's not just movies, televisions and video games that are going three-dimensional these days. Microchips are doing it, too.

Semiconductors aren't shifting into the third dimension because it’s fashionable, though. This shift is about continuing Moore’s Law, the relentless drive for higher performance that has driven the industry for four decades.

With three very different types of 3D construction in development today, it can be a confusing subject. Vertical chip structures, 3D device stacking, 3D chip packaging – what does it all mean?

We made this video to help demystify the subject. Did it help? Let me know in the comments below.

When it comes to microchip technology, transistors seem to get all the attention. But did you know that the transistor layer only makes up 10% of a modern logic chip?

The other 90% is made up of interconnect layers – the three-dimensional maze of copper wires that make connections between all those transistors and the outside world. From a volume perspective, that makes the dielectric insulator that supports all that copper the most important material in all of chipmaking!

With each technology node, the interconnects are squeezed closer together, increasing the potential for parasitic capacitance that slows the chip down and wastes power. To compensate, the dielectric has evolved from a simple glass-like material to a complex structure of nanoscale air pockets trapped in a carbon-silicon matrix.

In this video, Russ Perry explores the breakthroughs in dielectric technology that have enabled interconnect performance to keep pace with Moore’s Law while steadily increasing power-efficiency, the two keys to the success of mobile computing.

Stay tuned for the second episode, where Russ will discuss what the future has in store for the microchip's silent but high-tech majority.

May 4, 2011 may go down in history as a day that shook the chip industry to its core, literally. Anyone even remotely interested in technology must have caught Intel’s dramatic announcement on that day that 3-D transistors are now ready to enter high-volume manufacturing.

However, other leading players believe there’s plenty of development room left in two dimensions.

The debate about the relative merits of that third dimension has actually been going on for a while.
(I wrote about this very topic here almost a year ago.) Intel’s announcement, combined with the fact that the semiconductor industry is getting uncomfortably close to the physical limits of conventional transistor construction, is lending new urgency to the subject.

Applied Materials doesn’t make microchips. Our customers – the chipmakers – make them. But they use our machines and technologies to do so, and that gives us a unique perspective.

Two of Applied Materials’ leading technologists, Klaus Schuegraf, CTO of the semiconductor division and senior strategist Khaled Ahmed have written a fascinating article for IEEE Spectrum, exploring these competing technologies and the industry heavyweights lining up behind each one.

As Klaus and Khaled put it:

“Although it’s not yet clear which device architecture will win, what’s certain is that the CMOS transistor – the centerpiece of computer processors since the 1980s – will get an entirely new look.”

I highly recommend you click on over to IEEE Spectrum and read the whole article.

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Chipmaking is arguably the most complex manufacturing operation in human history. To illustrate this:

• A modern megafab – one that processes over a million wafers a year – contains hundreds of individual machines and turns out billions of finished chips a year
• It can take over 750 individual process steps to make a modern microprocessor
• The number of different types of chips being made simultaneously is growing while adding more layers to each one. As technology continues to progress the size of the chips are shrinking and manufacturing constraints are increasing

How is this complexity handled? By computers, of course, using a similarly complex piece of software called a manufacturing execution system (MES) which keeps track of every machine and every wafer in the fab.

At Applied Materials, we’ve taken software automation to the next level. Our SmartSched software doesn’t just react to changing fab conditions; it peers into the future. This video shows how it works.

Recently, I posted a video featuring Applied’s David Thompson explaining how Atomic Layer Deposition (ALD) works, and how it can be used to lay down critical transistor film layers just a few atoms thick.

However, ALD is just one of several techniques that chipmakers will use to overcome the challenges of engineering the nanoscale transistors at the heart of cutting edge semiconductor devices.

In the video above, Steven Hung, Ph.D. who specializes in integrating ALD into the transistor manufacturing process, dives deep into the chip to show what tomorrow’s transistors look like, how they work, and how Applied can help the industry meet the challenges of fabricating these ultra-tiny structures to make faster, more power-efficient microchips.

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